1. Field of the Invention
The present invention relates to a data processing apparatus and method for performing floating point addition, and in particular to a data processing apparatus and method for adding first and second n-bit significands of first and second floating point operands to produce an n-bit result.
2. Description of the Prior Art
A floating point number can be expressed as follows:±1.x*2y 
where: x=fraction                1.x=significand (also known as the mantissa)        y=exponent        
Floating point addition can take two forms, namely like-signed addition (LSA) or unlike-signed addition (USA). An LSA operation is performed if two floating point operands of the same sign are to be added, or if two floating point operands of different signs are to be subtracted. Similarly, a USA operation is to be performed if two floating point operands of different sign are to be added, or if two floating point operands of the same sign are to be subtracted. When referring in the present application to the addition of floating point operands and the addition of the n-bit significands of such operands, this should be taken as collectively referring to LSA or USA computations, and accordingly it will be appreciated that such a term covers both addition and subtraction processes.
When adding the n-bit significands of two floating point operands in order to produce an n-bit result, the following steps need to be performed:    1. A determination is made as to which of the two floating point operands is the largest.    2. The n-bit significand of the smaller operand is then aligned with the n-bit significand of the larger operand.    3. In the event of a USA operation, the smaller operand is inverted and a carry-in bit to subsequent adder logic is set. For an LSA operation, no such inversion is required, and the carry-in bit is not set.    4. The two significand values, manipulated as described above, are then added to produce a non-rounded sum.    5. The non-rounded sum is then normalised (shifted so that it has the form 1.x). The exponent is adjusted accordingly.    6. The bits of the non-rounded sum to the right of the least significant result bit (the result requires only the n most significant bits) are then evaluated to determine whether rounding is appropriate.    7. Then, a rounding increment is added to the significant bits of the result dependent on the rounding evaluation performed in step 6 above.    8. The rounded sum is then normalised (shifted so that it has the form 1.x). The exponent is adjusted accordingly.
With regard to the above sequence of steps, it has been found that not all additions require all of the above steps to be performed. Given this observation, it is known to provide a data processing apparatus which has two separate paths for performing floating point additions, one being referred to as the near path and the other being referred to as the far path.
In accordance with one known prior art technique, the exponent difference between the two input floating point operands is determined, and if the exponent difference is greater than one, then the addition is performed in the far path. Conversely, if the exponent difference is less than or equal to one, then the addition is performed in the near path. If the exponent difference is greater than one, then alignment logic needs to be provided to enable more than a non-trivial alignment to be performed, but the sum value produced will not require anything other than a non-trivial normalisation. Hence, the far path can be provided with alignment logic, but does not require any significant normalisation logic. Conversely, if the exponent difference is less than or equal to one, there is no need for any significant alignment logic, since only a trivial alignment will at most be required, but there is a requirement for normalisation logic, since when performing an unlike-signed addition massive cancellation may occur. Accordingly, to enable the resultant floating point value to be correctly normalised, it is then necessary to provide normalisation logic within the near path.
Accordingly, by providing a near path and a far path, the length of each path can be made shorter than would otherwise be the case if a single unitary path were provided for performing the floating point addition operation, and this can hence produce an increase in processing speed. For example, considering a pipelined processing logic example, the pipeline depth can be reduced by using a near path and a far path, which can give rise to an increase in processing speed when compared with a unitary processing path.
An adaptation of the above two-path implementation is to additionally use the far path for all like-signed additions. Hence, the near path is only used for unlike-signed additions whose exponent difference is less than or equal to one. When performing an unlike-signed addition, it is necessary to negate the smaller operand. Since the near path is only used for unlike-signed additions, then the smaller operand can be unconditionally negated in the near path. This slightly reduces the complexity of the near path.
Using either of the above two-path implementations, it is still necessary to provide rounding logic in both the near path and the far path to perform any appropriate rounding on the results of the addition performed in each path. U.S. Pat. No. 5,808,926 describes a variant of the second approach identified above, where the near path is only used when performing unlike-signed additions of operands which either have equal exponents, or have exponents that differ by one and for which the result of the addition operation requires shifting to be normalised. In situations where the result needs to be shifted to be normalised, this will mean that there are no bits to the right of the least significant bit of the result, and accordingly no rounding will ever be required. Accordingly, such an approach enables near path logic to be constructed which has no rounding logic within it.
The paper entitled “1-GHz HAL SPARC64 Dual Floating Point Unit with RAS Features” by A Naini et al, Proceedings of the 15th IEEE Symposium on Computer Architecture, 2001 also describes a data processing apparatus having a near processing path and a far processing path that adopts the approach set out in the above-mentioned U.S. Pat. No. 5,808,926.
Whilst the approach described in U.S. Pat. No. 5,808,926 removes the need for rounding logic in the near path, thus reducing latency and giving the near path the potential for requiring less power than the far path, it suffers from the problem that most additions need to be performed using the far path.
Accordingly, it would be desirable to provide a technique which enabled more addition operations to use the near path, whilst still allowing similar latency reductions and power savings to be achieved.